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525.712 - Advanced Computer Architecture Course Homepage

Instructor Information

Charles Cameron

Email: cameronc@usna.edu
Work Phone: (410) 293-6152
Home Phone: (410) 757-8876

Course Information

Course Description

This course covers topics essential to modern superscalar processor design. A review of pipelined processor design and hierarchical memory design is followed by advanced topics including the identification of parallelism in processes; multiple diversified functional units in a pipelined processor; static, dynamic, and hybrid branch prediction techniques; the Tomasulo algorithm for efficient resolution of true data dependencies; advanced data flow techniques with and without speculative execution; multiprocessor systems; and multithreaded processors.

Prerequisites

525.412 Computer Architecture or equivalent.

Course Goal

This course covers topics essential to modern superscalar processor design. A review of pipelined processor design and hierarchical memory design is followed by advanced topics including the identification of parallelism in processes; multiple diversified functional units in a pipelined processor; static, dynamic, and hybrid branch prediction techniques; the Tomasulo Algorithm for efficient resolution of true data dependencies; advanced data flow techniques with and without speculative execution; multiprocessor systems; and multithreaded processors. The course 525.412 Computer Architecture or an equivalent introduction to computer architecture is a prerequisite.

Course Objectives

  • Be able to analyze and apply techniques for static, dynamic, and hybrid branch prediction to problems in practical high-speed computer design.
  • Be able to use the Tomasulo Algorithm to identify and satisfy true data dependencies in the design of superscalar processors.
  • Be able to analyze and use various advanced data flow techniques, both with and without speculative execution, in the design of high-speed processors.
  • Be able to analyze and use techniques that guarantee cache coherence and correct sequential memory access across multiprocessor systems.

When This Course is Typically Offered

This course is offered in the spring semester at the Dorsey Center.

Syllabus

Topics Covered

  • Instruction set design, principles of measuring processor performance, instruction-level processing, and pipelined processor design.
  • Hierarchical memory systems, including cache memories, virtual memory, and input/output systems.
  • Superscalar processor design, including limits on scalar pipeline throughput and the organization of superscalar pipelines.
  • Branch prediction, register reuse, register renaming, Tomasulo's algorithm, memory data flow techniques.
  • Case study: the PowerPC
  • Case study: the Intel P6
  • Comparison of commercial superscalar designs, including early and recent efforts: Compaq/DEC Alpha, Hewlett-Packard PA-RISC, IBM POWER, various Intel processors, MIPS, PowerPC, and SPARC.
  • Static branch prediction techniques: single-direction prediction, backwards taken/forwards not-taken, Ball/Larus heuristics, profiling.
  • Dynamic branch prediction techniques: basic algorithms, tournament predictor, static predictor selection, multihybrid predictor.
  • Advanced register data flow techniques: value locality, redundant execution, instruction reuse, speculation.
  • Multiprocessor systems: fully shared memory, memory coherence, cache coherence, synchronization of multiple memories.
  • Multithreaded processors: fine- and coarse-grained multithreading; resolution of control, register, and memory data dependencies; fault detection; prefetching, branch resolution.

Student Assessment Criteria

Homework 10%
Term paper 10%
Quizzes 20%
Midterm Test 30%
Final Exam 30%

Participation Expectations

Short quizzes will be given every week or two.  A term paper will be required on one of a list of topics pertinent to the subject.  In-class discussions and group activities will help to keep the course more interesting.

Textbooks

Textbook information for this course is available online through the MBS Direct Virtual Bookstore.

Course Notes

There are no notes for this course.

Final Words from the Instructor

Textbook:  John Paul Shen and Mikko H. Lipasti, Modern Processor Design: Fundamentals of Superscalar Processors, McGraw Hill, 2005.

Term Specific Course Website

http://www.apl.jhu.edu/Notes/Cameron/525.712/

(Last Modified: 11-15-2008 at 6:20:54 AM)